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| kinetis kl46 sub-family 48 mhz cortex-m0+ based microcontroller designed with efficiency in mind. compatible with all other kinetis l families as well as kinetis k4x family. general purpose mcu with usb 2.0 and segment lcd, featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution. this product offers: ? run power consumption down to 50 a/mhz in very low power run mode ? static power consumption down to 2 a with full state retention and 4.5 s wakeup ? ultra-efficient cortex-m0+ processor running up to 48 mhz with industry leading throughput ? memory option is up to 256 kb flash and 32 kb ram ? energy-saving architecture is optimized for low power with 90 nm tfs technology, clock and power gating techniques, and zero wait state flash memory controller performance ? 48 mhz arm ? cortex ? -m0+ core memories and memory interfaces ? up to 256 kb program flash memory ? up to 32 kb sram system peripherals ? nine low-power modes to provide power optimization based on application requirements ? cop software watchdog ? 4-channel dma controller, supporting up to 63 request sources ? low-leakage wakeup unit ? swd debug interface and micro trace buffer ? bit manipulation engine clocks ? 32 khz to 40 khz or 3 mhz to 32 mhz crystal oscillator ? multi-purpose clock source operating characteristics ? voltage range: 1.71 to 3.6 v ? flash write voltage range: 1.71 to 3.6 v ? temperature range (ambient): -40 to 105c human-machine interface ? segment lcd controller supporting up to 47 frontplanes and 8 backplanes, or 51 frontplanes and 4 backplanes ? low-power hardware touch sensor interface (tsi) ? up to 84 general-purpose input/output (gpio) communication interfaces ? usb full-/low-speed on-the-go controller with on- chip transceiver and 5 v to 3.3 v regulator ? two 16-bit spi modules ? i2s (sai) module ? one low power uart module ? two uart modules ? two i2c module analog modules ? 16-bit sar adc ? 12-bit dac ? analog comparator (cmp) containing a 6-bit dac and programmable reference input timers ? six channel timer/pwm (tpm) ? two 2-channel timer/pwm modules mkl46zxxxvlh4 mkl46z256vmp4 mkl46zxxxvll4 mkl46zxxxvmc4 64-pin lqfp (lh) 10 x 10 x 1.4 pitch 0.5 mm 64-pin mapbga (mp) 5 x 5 x 1.23 pitch 0.5 mm 100-pin lqfp (ll) 14 x 14 x 1.4 pitch 0.5 mm 121-pin mapbga (mp) 8 x 8 x 0.8 pitch 0.65 mm freescale semiconductor, inc. document number: KL46P121M48SF4 data sheet: technical data rev 5 08/2014 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012C2014 freescale semiconductor, inc. all rights reserved.
? periodic interrupt timers ? 16-bit low-power timer (lptmr) ? real time clock security and integrity modules ? 80-bit unique identification number per chip ordering information 1 part number memory maximum number of i\o's flash (kb) sram (kb) mkl46z128vlh4 128 16 50 mkl46z256vlh4 256 32 50 mkl46z256vmp4 256 32 50 mkl46z128vll4 128 16 84 mkl46z256vll4 256 32 84 mkl46z128vmc4 128 16 84 mkl46z256vmc4 256 32 84 1. to confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search. related resources type description resource selector guide the freescale solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. KL46P121M48SF4rm 1 data sheet the data sheet includes electrical characteristics and signal connections. KL46P121M48SF4 1 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_l_ x n40h 2 package drawing package dimensions are provided in package drawings. lqfp 64-pin: 98ass23234w 1 mapbga 64-pin: 98asa00420d 1 lqfp 100-pin: 98ass23308w 1 mapbga 121-pin: 98asa00344d 1 1. to find the associated resource, go to http://www.freescale.com and perform a search using this term. 2. to find the associated resource, go to http://www.freescale.com and perform a search using this term with the x replaced by the revision of the device you are using. 2 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table of contents 1 ratings.................................................................................. 4 1.1 thermal handling ratings............................................... 4 1.2 moisture handling ratings............................................... 4 1.3 esd handling ratings..................................................... 4 1.4 voltage and current operating ratings............................ 4 2 general................................................................................. 5 2.1 ac electrical characteristics........................................... 5 2.2 nonswitching electrical specifications............................ 6 2.2.1 voltage and current operating requirements...... 6 2.2.2 lvd and por operating requirements.............. 6 2.2.3 voltage and current operating behaviors........... 7 2.2.4 power mode transition operating behaviors....... 8 2.2.5 power consumption operating behaviors........... 9 2.2.6 emc radiated emissions operating behaviors... 15 2.2.7 designing with radiated emissions in mind........ 16 2.2.8 capacitance attributes....................................... 16 2.3 switching specifications................................................. 16 2.3.1 device clock specifications................................ 16 2.3.2 general switching specifications........................ 17 2.4 thermal specifications................................................... 17 2.4.1 thermal operating requirements........................ 17 2.4.2 thermal attributes.............................................. 17 3 peripheral operating requirements and behaviors................ 18 3.1 core modules................................................................ 18 3.1.1 swd electricals ................................................. 18 3.2 system modules............................................................ 20 3.3 clock modules............................................................... 20 3.3.1 mcg specifications............................................ 20 3.3.2 oscillator electrical specifications...................... 22 3.4 memories and memory interfaces................................. 24 3.4.1 flash electrical specifications............................ 24 3.5 security and integrity modules....................................... 26 3.6 analog............................................................................ 26 3.6.1 adc electrical specifications.............................. 26 3.6.2 cmp and 6-bit dac electrical specifications...... 31 3.6.3 12-bit dac electrical characteristics.................. 33 3.7 timers............................................................................ 36 3.8 communication interfaces............................................. 36 3.8.1 usb electrical specifications.............................. 36 3.8.2 usb vreg electrical specifications................... 37 3.8.3 spi switching specifications............................... 37 3.8.4 inter-integrated circuit interface (i2c) timing..... 42 3.8.5 uart................................................................. 43 3.8.6 i2s/sai switching specifications........................ 43 3.9 human-machine interfaces (hmi).................................. 47 3.9.1 tsi electrical specifications................................ 47 3.9.2 lcd electrical characteristics............................. 48 4 dimensions........................................................................... 49 4.1 obtaining package dimensions...................................... 49 5 pinout.................................................................................... 50 5.1 kl46 signal multiplexing and pin assignments............. 50 5.2 kl46 pinouts.................................................................. 54 6 ordering parts....................................................................... 58 6.1 determining valid orderable parts.................................. 58 7 part identification................................................................... 59 7.1 description..................................................................... 59 7.2 format........................................................................... 59 7.3 fields............................................................................. 59 7.4 example......................................................................... 60 8 terminology and guidelines.................................................. 60 8.1 definition: operating requirement.................................. 60 8.2 definition: operating behavior....................................... 60 8.3 definition: attribute........................................................ 61 8.4 definition: rating........................................................... 61 8.5 result of exceeding a rating.......................................... 61 8.6 relationship between ratings and operating requirements.................................................................. 62 8.7 guidelines for ratings and operating requirements........ 62 8.8 definition: typical value................................................. 63 8.9 typical value conditions................................................. 64 9 revision history..................................................................... 64 kinetis kl46 sub-family, rev5 08/2014. 3 freescale semiconductor, inc. 1 ratings 1.1 thermal handling ratings table 1. thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings table 2. moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings table 3. esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model C2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model C500 +500 v 2 i lat latch-up current at ambient temperature of 105 c C100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . ratings 4 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 1.4 voltage and current operating ratings table 4. voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 120 ma v io io pin input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb_dp usb_dp input voltage C0.3 3.63 v v usb_dm usb_dm input voltage C0.3 3.63 v v regin usb regulator input C0.3 6.0 v 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. ? c l =30 pf loads ? slew rate disabled ? normal drive strength general kinetis kl46 sub-family, rev5 08/2014. 5 freescale semiconductor, inc. 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 5. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio io pin negative dc injection current single pin ? v in < v ss -0.3v -3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents of 16 contiguous pins ? negative current injection -25 ma v odpu open drain pullup voltage level v dd v dd v 2 v ram v dd voltage required to retain ram 1.2 v 1. all i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v io_min (= v ss -0.3 v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r = (v io_min - v in )/|i icio |. 2. open drain outputs must be pulled to v dd . 2.2.2 lvd and por operating requirements table 6. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v table continues on the next page... general 6 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 6. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvdh falling low-voltage detect threshold high range (lvdv = 01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv = 00) ? level 2 falling (lvwv = 01) ? level 3 falling (lvwv = 10) ? level 4 falling (lvwv = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv = 00) ? level 2 falling (lvwv = 01) ? level 3 falling (lvwv = 10) ? level 4 falling (lvwv = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage 2.2.3 voltage and current operating behaviors table 7. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage normal drive pad (except reset_b) ? 2.7 v v dd 3.6 v, i oh = -5 ma ? 1.71 v v dd 2.7 v, i oh = -2.5 ma v dd C 0.5 v dd C 0.5 v v 1 , 2 v oh output high voltage high drive pad (except reset_b) ? 2.7 v v dd 3.6 v, i oh = -20 ma ? 1.71 v v dd 2.7 v, i oh = -10 ma v dd C 0.5 v dd C 0.5 v v 1 , 2 i oht output high current total for all ports 100 ma table continues on the next page... general kinetis kl46 sub-family, rev5 08/2014. 7 freescale semiconductor, inc. table 7. voltage and current operating behaviors (continued) symbol description min. max. unit notes v ol output low voltage normal drive pad ? 2.7 v v dd 3.6 v, i ol = 5 ma ? 1.71 v v dd 2.7 v, i ol = 2.5 ma 0.5 0.5 v v 1 v ol output low voltage high drive pad ? 2.7 v v dd 3.6 v, i ol = 20 ma ? 1.71 v v dd 2.7 v, i ol = 10 ma 0.5 0.5 v v 1 i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 a 3 i in input leakage current (per pin) at 25 c 0.025 a 3 i in input leakage current (total all pins) for full temperature range a 3 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 4 1. ptb0, ptb1, ptd6, and ptd7 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. the reset pin only contains an active pull down device when configured as the reset signal or as a gpio. when configured as a gpio output, it acts as a pseudo open drain output. 3. measured at v dd = 3.6 v 4. measured at v dd supply voltage = v dd min and vinput = v ss 2.2.4 power mode transition operating behaviors all specifications except t por and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 48 mhz ? bus and flash clock = 24 mhz ? fei clock mode por and vllsx run recovery use fei clock mode at the default cpu and system frequency of 21 mhz, and a bus and flash clock frequency of 10.5 mhz. table 8. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 table continues on the next page... general 8 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 8. power mode transition operating behaviors (continued) symbol description min. typ. max. unit notes ? vlls0 run 113 124 s ? vlls1 run 112 124 s ? vlls3 run 53 60 s ? lls run 4.5 5.0 s ? vlps run 4.5 5.0 s ? stop run 4.5 5.0 s 1. normal boot (ftfa_fopt[lpboot]=11). 2.2.5 power consumption operating behaviors the maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). table 9. power consumption operating behaviors symbol description typ. max unit note i dda analog supply current see note ma 1 i dd_runco_ cm run mode current in compute operation - 48 mhz core / 24 mhz flash/ bus disabled, lptmr running using 4 mhz internal reference clock, coremark? benchmark code executing from flash, at 3.0 v 6.7 ma 2 i dd_runco run mode current in compute operation - 48 mhz core / 24 mhz flash / bus clock disabled, code of while(1) loop executing from flash, at 3.0 v 4.5 5.1 ma 3 i dd_run run mode current - 48 mhz core / 24 mhz bus and flash, all peripheral clocks disabled, code executing from flash at 1.8 v 5.6 6.3 ma 3 at 3.0 v 5.4 6.0 ma i dd_run run mode current - 48 mhz core / 24 mhz bus and flash, all peripheral clocks enabled, code executing from flash, at 1.8 v 6.9 7.3 ma 3 , 4 table continues on the next page... general kinetis kl46 sub-family, rev5 08/2014. 9 freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description typ. max unit note run mode current - 48 mhz core / 24 mhz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 v at 25 c 6.9 7.1 ma at 125 c 7.3 7.6 ma i dd_wait wait mode current - core disabled / 48 mhz system / 24 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 v 2.9 3.5 ma 3 i dd_wait wait mode current - core disabled / 24 mhz system / 24 mhz bus / flash disabled (flash doze enabled), wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 2.2 2.8 ma 3 i dd_pstop2 stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 mhz bus, at 3.0 v 1.6 2.1 ma 3 i dd_vlprco _cm very-low-power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, lptmr running with 4 mhz internal reference clock, coremark benchmark code executing from flash, at 3.0 v 798 a 5 i dd_vlprco very low power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, code executing from flash, at 3.0 v 167 336 a 6 i dd_vlpr very low power run mode current - 4 mhz core / 0.8 mhz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 v 192 354 a 6 i dd_vlpr very low power run mode current - 4 mhz core / 0.8 mhz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 v 257 431 a 4 , 6 i dd_vlpw very low power wait mode current - core disabled / 4 mhz system / 0.8 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 v 112 286 a 6 i dd_stop stop mode current at 3.0 v at 25 c 306 328 a at 50 c 322 349 a at 70 c 348 382 a at 85 c 384 433 a at 105 c 481 578 a i dd_vlps very-low-power stop mode current at 3.0 v at 25 c 2.71 5.03 a at 50 c 7.05 11.94 a at 70 c 15.80 26.87 a table continues on the next page... general 10 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description typ. max unit note at 85 c 29.60 47.30 a at 105 c 69.13 106.04 a i dd_lls low leakage stop mode current at 3.0 v at 25 c 2.00 2.7 a at 50 c 3.96 5.14 a at 70 c 7.77 10.71 a at 85 c 14.15 18.79 a at 105 c 33.20 43.67 a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v at 25 c 1.5 2.2 a at 50 c 2.83 3.55 a at 70 c 5.53 7.26 a at 85 c 9.92 12.71 a at 105 c 22.90 29.23 a i dd_vlls1 very low-leakage stop mode 1 current at 3.0v at 25 c 0.71 1.2 a at 50 c 1.27 1.9 a at 70 c 2.48 3.51 a at 85 c 4.65 6.29 a at 105 c 11.55 14.34 a i dd_vlls0 very low-leakage stop mode 0 current (smc_stopctrl[porpo] = 0) at 3.0 v at 25 c 0.41 0.9 a at 50 c 0.96 1.56 a at 70 c 2.17 3.1 a at 85 c 4.35 5.32 a at 105 c 11.24 14.00 a i dd_vlls0 very low-leakage stop mode 0 current (smc_stopctrl[porpo] = 1) at 3.0 v at 25 c 0.23 0.69 a 7 at 50 c 0.77 1.35 a at 70 c 1.98 2.52 a at 85 c 4.16 5.14 a at 105 c 11.05 13.80 a 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. mcg configured for pee mode. coremark benchmark compiled using iar 6.40 with optimization level high, optimized for balanced. 3. mcg configured for fei mode. 4. incremental current consumption from peripheral activity is not included. 5. mcg configured for blpi mode. coremark benchmark compiled using iar 6.40 with optimization level high, optimized for balanced. 6. mcg configured for blpi mode. 7. no brownout. general kinetis kl46 sub-family, rev5 08/2014. 11 freescale semiconductor, inc. table 10. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 a i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 440 490 540 560 570 580 na vlls3 440 490 540 560 570 580 lls 490 490 540 560 570 680 vlps 510 560 560 560 610 680 stop 510 560 560 560 610 680 i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) 66 66 66 66 66 66 a oscerclk (4 mhz external crystal) 214 237 246 254 260 268 i tpm tpm peripheral adder measured by placing the device in stop or vlps mode with selected clock source configured for output compare generating 100 hz clock signal. no load is placed on the i/o generating the clock signal. includes selected clock source and i/o switching currents. mcgirclk (4 mhz internal reference clock) 86 86 86 86 86 86 a oscerclk (4 mhz external crystal) 235 256 265 274 280 287 table continues on the next page... general 12 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 10. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a i lcd lcd peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the osc0_cr[erefsten, erefsten] bits. vireg disabled, resistor bias network enabled, 1/8 duty cycle, 8 x 36 configuration for driving 288 segments, 32 hz frame rate, no lcd glass connected. includes erclk32k (32 khz external crystal) power consumption. 5 5 5 5 5 5 a 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe for run mode, and blpe for vlpr mode ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfa general kinetis kl46 sub-family, rev5 08/2014. 13 freescale semiconductor, inc. 4.00e-03 5.00e-03 6.00e-03 7.00e-03 8.00e-03 all off temperature = 25, v dd = 3, cache = enable, code residence = flash, clocking mode = fbe all peripheral clk gates 000.00e+00 1.00e-03 2.00e-03 3.00e-03 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 all on clk ratio flash-core core freq (mhz) current consumption on v dd (a) run mode current vs core frequency figure 3. run mode supply current vs. core frequency general 14 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 200.00e-06 250.00e-06 300.00e-06 350.00e-06 vlpr mode current vs core frequency temperature = 25, v dd = 3, cache = enable, code residence = flash, clocking mode = blpe all peripheral clk gates 000.00e+00 50.00e-06 100.00e-06 150.00e-06 '1 - 1 '1 - 2 '1 - 2 '1 - 4 1 2 4 all off all on clk ratio flash-core core freq (mhz) current consumption on v dd (a) figure 4. vlpr mode current vs. core frequency 2.2.6 emc radiated emissions operating behaviors table 11. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 12 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 8 dbv v re3 radiated emissions voltage, band 3 150C500 7 dbv v re4 radiated emissions voltage, band 4 500C1000 4 dbv v re_iec iec level 0.15C1000 m 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 8 mhz (crystal), f sys = 48 mhz, f bus = 24 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method general kinetis kl46 sub-family, rev5 08/2014. 15 freescale semiconductor, inc. 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 12. capacitance attributes symbol description min. max. unit c in input capacitance 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 13. device clock specifications symbol description min. max. unit normal run mode f sys system and core clock 48 mhz f bus bus clock 24 mhz f flash flash clock 24 mhz f sys_usb system and core clock when full speed usb in operation 20 mhz f lptmr lptmr clock 24 mhz vlpr and vlps modes 1 f sys system and core clock 4 mhz f bus bus clock 1 mhz f flash flash clock 1 mhz f lptmr lptmr clock 2 24 mhz f erclk external reference clock 16 mhz f lptmr_erclk lptmr external reference clock 16 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 16 mhz f tpm tpm asynchronous clock 8 mhz f uart0 uart0 asynchronous clock 8 mhz general 16 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 1. the frequency limitations in vlpr and vlps modes here override any frequency specification listed in the timing specification for any other module. these same frequency limits apply to vlps, whether vlps was entered from run or from vlpr. 2. the lptmr can be clocked at this speed in vlpr or vlps only when the source is an external pin. 2.3.2 general switching specifications these general-purpose specifications apply to all signals configured for gpio and uart signals. table 14. general switching specifications description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 16 ns 2 port rise and fall time 36 ns 3 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 75 pf load 2.4 thermal specifications 2.4.1 thermal operating requirements table 15. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c general kinetis kl46 sub-family, rev5 08/2014. 17 freescale semiconductor, inc. 2.4.2 thermal attributes table 16. thermal attributes board type symbol description 121 mapbg a 100 lqfp 64 lqfp 64 mapbg a unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 94 64 69 49.8 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 57 51 51 42.3 c/w single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 81 54 58 40.9 c/w four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 53 45 44 37.7 c/w r jb thermal resistance, junction to board 40 37 33 39.2 c/w 2 r jc thermal resistance, junction to case 30 19 19 50.3 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 8 4 4 2.2 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 3 peripheral operating requirements and behaviors 3.1 core modules peripheral operating requirements and behaviors 18 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 3.1.1 swd electricals table 17. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 swd_clk frequency of operation ? serial wire debug 0 25 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 5. serial wire clock input timing peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 19 freescale semiconductor, inc. j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 6. serial wire data timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules 3.3.1 mcg specifications table 18. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal v dd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using c3[sctrim] and c4[scftrim] 0.3 0.6 %f dco 1 table continues on the next page... peripheral operating requirements and behaviors 20 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 18. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 3 %f dco 1 , 2 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70 c 0.4 1.5 %f dco 1 , 2 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal v dd and 25 c 4 mhz f intf_ft frequency deviation of internal reference clock (fast clock) over temperature and voltage factory trimmed at nominal v dd and 25 c +1/-2 3 %f intf_ft 2 f intf_t internal reference frequency (fast clock) user trimmed at nominal v dd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs = 00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs = 01) 1280 f fll_ref 40 41.94 48 mhz f dco_t_dmx3 2 dco output frequency low range (drs = 00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs = 01) 1464 f fll_ref 47.97 mhz j cyc_fll fll period jitter ? f vco = 48 mhz 180 ps 7 t fll_acquire fll target frequency acquisition time 1 ms 8 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current ? pll at 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 9 i pll pll operating current ? pll at 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 9 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 100 mhz 120 ps ps 10 table continues on the next page... peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 21 freescale semiconductor, inc. table 18. mcg specifications (continued) symbol description min. typ. max. unit notes j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 48 mhz ? f vco = 100 mhz 1350 600 ps ps 10 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 11 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. the deviation is relative to the factory trimmed frequency at nominal v dd and 25 c, f ints_ft . 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 0. 4. the resulting system clock frequencies must not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature must be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification is based on standard deviation (rms) of period or frequency. 8. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. excludes any oscillator currents that are also consuming power while pll is in operation. 10. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 11. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 oscillator electrical specifications 3.3.2.1 oscillator dc electrical specifications table 19. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz 500 200 300 950 1.2 na a a a ma 1 table continues on the next page... peripheral operating requirements and behaviors 22 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 19. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes ? 24 mhz ? 32 mhz 1.5 ma i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 23 freescale semiconductor, inc. 3. c x ,c y can be provided by using the integrated capacitors when the low frequency oscillator (range = 00) is used. for all other cases external capacitors must be used. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 oscillator frequency specifications table 20. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high- frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 48 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 3.4 memories and memory interfaces 3.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. peripheral operating requirements and behaviors 24 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 21. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk128k erase block high-voltage time for 128 kb 52 452 ms 1 t hversall erase all high-voltage time 52 452 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 22. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk128k read 1s block execution time ? 128 kb program flash 1.7 ms t rd1sec1k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersblk128k erase flash block execution time ? 128 kb program flash 88 600 ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 175 1300 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 25 freescale semiconductor, inc. 3.4.1.3 flash high voltage current behaviors table 23. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.4.1.4 reliability specifications table 24. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40 c t j 125 c. 3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog 3.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 25 and table 26 are achievable on the differential pins adcx_dp0, adcx_dm0. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. peripheral operating requirements and behaviors 26 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 3.6.1.1 16-bit adc operating conditions table 25. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 * vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 18.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 27 freescale semiconductor, inc. r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 7. adc input impedance equivalency diagram 3.6.1.2 16-bit adc electrical characteristics table 26. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors 28 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 26. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes inl integral non- linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 29 freescale semiconductor, inc. 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 8. typical enob vs. adc_clk for 16-bit differential mode typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 9. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors 30 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 3.6.2 cmp and 6-bit dac electrical specifications table 27. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 31 freescale semiconductor, inc. 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 10. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors 32 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 11. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.6.3 12-bit dac electrical characteristics 3.6.3.1 12-bit dac operating requirements table 28. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 33 freescale semiconductor, inc. 3.6.3.2 12-bit dac operating behaviors table 29. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 250 a i dda_dach p supply current high-speed mode 900 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device peripheral operating requirements and behaviors 34 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 12. typical inl error vs. digital code peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 35 freescale semiconductor, inc. temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 13. offset at half scale vs. temperature 3.7 timers see general switching specifications . 3.8 communication interfaces 3.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit usb.org . peripheral operating requirements and behaviors 36 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. note the mcgpllclk meets the usb jitter specifications for certification with the use of an external clock/crystal for both device and host modes. the mcgfllclk does not meet the usb jitter specifications for certification. 3.8.2 usb vreg electrical specifications table 30. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 125 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 10 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25 c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 37 freescale semiconductor, inc. 3.8.3 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pf maximum load on all spi pins. table 31. spi master mode timing on slew rate disabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 18 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 15 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph table 32. spi master mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 96 ns 7 t hi data hold time (inputs) 0 ns table continues on the next page... peripheral operating requirements and behaviors 38 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 32. spi master mode timing on slew rate enabled pads (continued) num. symbol description min. max. unit note 8 t v data valid (after spsck edge) 52 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 14. spi master mode timing (cpha = 0) peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 39 freescale semiconductor, inc. < table 34. spi slave mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation 0 f periph /4 hz 1 2 t spsck spsck period 4 x t periph ns 2 3 t lead enable lead time 1 t periph 4 t lag enable lag time 1 t periph 5 t wspsck clock (spsck) high or low time t periph - 30 ns 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 122 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 16. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 41 freescale semiconductor, inc. 2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 17. spi slave mode timing (cpha = 1) 3.8.4 inter-integrated circuit interface (i2c) timing table 35. i2c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 1 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 2 3.45 3 0 4 0.9 2 s data set-up time t su ; dat 250 5 100 3 , 6 ns rise time of sda and scl signals t r 1000 20 +0.1c b 7 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 6 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the maximum scl clock frequency in fast mode with maximum bus loading can only achieved when using the high drive pins (see voltage and current operating behaviors ) or when using the normal drive pins and vdd 2.7 v peripheral operating requirements and behaviors 42 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 2. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 3. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 4. input signal slew = 10 ns and output load = 50 pf 5. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 6. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 7. c b = total capacitance of the one bus line in pf. ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 18. timing definition for fast and standard mode devices on the i 2 c bus 3.8.5 uart see general switching specifications . 3.8.6 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 43 freescale semiconductor, inc. 3.8.6.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 36. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15.5 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 19 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 26 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 19. i2s/sai timing master modes peripheral operating requirements and behaviors 44 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 37. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 10 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 33 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 10 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 28 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 20. i2s/sai timing slave modes 3.8.6.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 45 freescale semiconductor, inc. table 38. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 75 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 21. i2s/sai timing master modes table 39. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns table continues on the next page... peripheral operating requirements and behaviors 46 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 39. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 87 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 22. i2s/sai timing slave modes 3.9 human-machine interfaces (hmi) 3.9.1 tsi electrical specifications table 40. tsi electrical specifications symbol description min. typ. max. unit tsi_runf fixed power consumption in run mode 100 a table continues on the next page... peripheral operating requirements and behaviors kinetis kl46 sub-family, rev5 08/2014. 47 freescale semiconductor, inc. table 40. tsi electrical specifications (continued) symbol description min. typ. max. unit tsi_runv variable power consumption in run mode (depends on oscillator's current selection) 1.0 128 a tsi_en power consumption in enable mode 100 a tsi_dis power consumption in disable mode 1.2 a tsi_ten tsi analog enable time 66 s tsi_cref tsi reference capacitor 1.0 pf tsi_dvolt voltage variation of vp & vm around nominal values 0.19 1.03 v 3.9.2 lcd electrical characteristics table 41. lcd electricals symbol description min. typ. max. unit notes f frame lcd frame frequency ? gcr[ffr]=0 ? gcr[ffr]=1 23.3 46.6 73.1 146.2 hz hz c lcd lcd charge pump capacitance nominal value 100 nf 1 c bylcd lcd bypass capacitance nominal value 100 nf 1 c glass lcd glass capacitance 2000 8000 pf 2 v ireg v ireg ? rvtrim=0000 ? rvtrim=1000 ? rvtrim=0100 ? rvtrim=1100 ? rvtrim=0010 ? rvtrim=1010 ? rvtrim=0110 ? rvtrim=1110 ? rvtrim=0001 ? rvtrim=1001 ? rvtrim=0101 ? rvtrim=1101 ? rvtrim=0011 ? rvtrim=1011 0.91 0.92 0.93 0.94 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.05 1.06 1.07 1.08 v 3 table continues on the next page... peripheral operating requirements and behaviors 48 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 41. lcd electricals (continued) symbol description min. typ. max. unit notes ? rvtrim=0111 ? rvtrim=1111 1.09 rtrim v ireg trim resolution 3.0 % v ireg i vireg v ireg current adder rven = 1 1 a 4 i rbias rbias current adder ? ladj = 10 or 11 high load (lcd glass capacitance 8000 pf) ? ladj = 00 or 01 low load (lcd glass capacitance 2000 pf) 10 1 a a r rbias rbias resistor values ? ladj = 10 or 11 high load (lcd glass capacitance 8000 pf) ? ladj = 00 or 01 low load (lcd glass capacitance 2000 pf) 0.28 2.98 m m vll1 vll1 voltage v ireg v 5 vll2 vll2 voltage 2 x v ireg v 5 vll3 vll3 voltage 3 x v ireg v 5 vll1 vll1 voltage v dda / 3 v 6 vll2 vll2 voltage v dda / 1.5 v 6 vll3 vll3 voltage v dda v 6 1. the actual value used could vary with tolerance. 2. for highest glass capacitance values, lcd_gcr[ladj] should be configured as specified in the lcd controller chapter within the device's reference manual. 3. v ireg maximum should never be externally driven to any level other than v dd - 0.15 v 4. 2000 pf load lcd, 32 hz frame frequency 5. vll1, vll2 and vll3 are a function of v ireg only when the regulator is enabled (gcr[rven]=1) and the charge pump is enabled (gcr[cpsel]=1). 6. vll1, vll2 and vll3 are a function of v dda only under either of the following conditions: ? the charge pump is enabled (gcr[cpsel]=1), the regulator is disabled (gcr[rven]=0), and vll3 = v dda through the internal power switch (gcr[vsupply]=0). ? the resistor bias string is enabled (gcr[cpsel]=0), the regulator is disabled (gcr[rven]=0), and vll3 is connected to v dda externally (gcr[vsupply]=1). 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. dimensions kinetis kl46 sub-family, rev5 08/2014. 49 freescale semiconductor, inc. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 64-pin lqfp 98ass23234w 64-pin mapbga 98asa00420d 100-pin lqfp 98ass23308w 121-pin mapbga 98asa00344d 5 pinout 5.1 kl46 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 121 bga 100 lqfp 64 bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 e4 1 a1 1 pte0 disabled lcd_p48 pte0 spi1_miso uart1_tx rtc_ clkout cmp0_out i2c1_sda lcd_p48 e3 2 b1 2 pte1 disabled lcd_p49 pte1 spi1_mosi uart1_rx spi1_miso i2c1_scl lcd_p49 e2 3 pte2 disabled lcd_p50 pte2 spi1_sck lcd_p50 f4 4 pte3 disabled lcd_p51 pte3 spi1_miso spi1_mosi lcd_p51 h7 5 pte4 disabled lcd_p52 pte4 spi1_pcs0 lcd_p52 g4 6 pte5 disabled lcd_p53 pte5 lcd_p53 f3 7 pte6 disabled lcd_p54 pte6 i2s0_mclk audiousb_ sof_out lcd_p54 e6 8 3 vdd vdd vdd g7 9 c4 4 vss vss vss l6 vss vss vss f1 10 e1 5 usb0_dp usb0_dp usb0_dp f2 11 d1 6 usb0_dm usb0_dm usb0_dm g1 12 e2 7 vout33 vout33 vout33 g2 13 d2 8 vregin vregin vregin h1 14 pte16 adc0_dp1/ adc0_se1 lcd_p55/ adc0_dp1/ adc0_se1 pte16 spi0_pcs0 uart2_tx tpm_ clkin0 lcd_p55 pinout 50 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 121 bga 100 lqfp 64 bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 h2 15 pte17 adc0_dm1/ adc0_se5a lcd_p56/ adc0_dm1/ adc0_se5a pte17 spi0_sck uart2_rx tpm_ clkin1 lptmr0_ alt3 lcd_p56 j1 16 pte18 adc0_dp2/ adc0_se2 lcd_p57/ adc0_dp2/ adc0_se2 pte18 spi0_mosi i2c0_sda spi0_miso lcd_p57 j2 17 pte19 adc0_dm2/ adc0_se6a lcd_p58/ adc0_dm2/ adc0_se6a pte19 spi0_miso i2c0_scl spi0_mosi lcd_p58 k1 18 g1 9 pte20 adc0_dp0/ adc0_se0 lcd_p59/ adc0_dp0/ adc0_se0 pte20 tpm1_ch0 uart0_tx lcd_p59 k2 19 f1 10 pte21 adc0_dm0/ adc0_se4a lcd_p60/ adc0_dm0/ adc0_se4a pte21 tpm1_ch1 uart0_rx lcd_p60 l1 20 g2 11 pte22 adc0_dp3/ adc0_se3 adc0_dp3/ adc0_se3 pte22 tpm2_ch0 uart2_tx l2 21 f2 12 pte23 adc0_dm3/ adc0_se7a adc0_dm3/ adc0_se7a pte23 tpm2_ch1 uart2_rx f5 22 f4 13 vdda vdda vdda g5 23 g4 14 vrefh vrefh vrefh g6 24 g3 15 vrefl vrefl vrefl f6 25 f3 16 vssa vssa vssa l3 26 h1 17 pte29 cmp0_in5/ adc0_se4b cmp0_in5/ adc0_se4b pte29 tpm0_ch2 tpm_ clkin0 k5 27 h2 18 pte30 dac0_out/ adc0_se23/ cmp0_in4 dac0_out/ adc0_se23/ cmp0_in4 pte30 tpm0_ch3 tpm_ clkin1 l4 28 h3 19 pte31 disabled pte31 tpm0_ch4 l5 29 vss vss vss k6 30 vdd vdd vdd h5 31 h4 20 pte24 disabled pte24 tpm0_ch0 i2c0_scl j5 32 h5 21 pte25 disabled pte25 tpm0_ch1 i2c0_sda h6 33 pte26 disabled pte26 tpm0_ch5 rtc_ clkout usb_clkin j6 34 d3 22 pta0 swd_clk tsi0_ch1 pta0 tpm0_ch5 swd_clk h8 35 d4 23 pta1 disabled tsi0_ch2 pta1 uart0_rx tpm2_ch0 j7 36 e5 24 pta2 disabled tsi0_ch3 pta2 uart0_tx tpm2_ch1 h9 37 d5 25 pta3 swd_dio tsi0_ch4 pta3 i2c1_scl tpm0_ch0 swd_dio j8 38 g5 26 pta4 nmi_b tsi0_ch5 pta4 i2c1_sda tpm0_ch1 nmi_b k7 39 f5 27 pta5 disabled pta5 usb_clkin tpm0_ch2 i2s0_tx_ bclk e5 vdd vdd vdd g3 vss vss vss k3 40 pta6 disabled pta6 tpm0_ch3 pinout kinetis kl46 sub-family, rev5 08/2014. 51 freescale semiconductor, inc. 121 bga 100 lqfp 64 bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 h4 41 pta7 disabled pta7 tpm0_ch4 k8 42 h6 28 pta12 disabled pta12 tpm1_ch0 i2s0_txd0 l8 43 g6 29 pta13 disabled pta13 tpm1_ch1 i2s0_tx_fs k9 44 pta14 disabled pta14 spi0_pcs0 uart0_tx i2s0_rx_ bclk i2s0_txd0 l9 45 pta15 disabled pta15 spi0_sck uart0_rx i2s0_rxd0 j10 46 pta16 disabled pta16 spi0_mosi spi0_miso i2s0_rx_fs i2s0_rxd0 h10 47 pta17 disabled pta17 spi0_miso spi0_mosi i2s0_mclk l10 48 g7 30 vdd vdd vdd k10 49 h7 31 vss vss vss l11 50 h8 32 pta18 extal0 extal0 pta18 uart1_rx tpm_ clkin0 k11 51 g8 33 pta19 xtal0 xtal0 pta19 uart1_tx tpm_ clkin1 lptmr0_ alt1 j11 52 f8 34 pta20 reset_b pta20 reset_b g11 53 f7 35 ptb0/ llwu_p5 lcd_p0/ adc0_se8/ tsi0_ch0 lcd_p0/ adc0_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl tpm1_ch0 lcd_p0 g10 54 f6 36 ptb1 lcd_p1/ adc0_se9/ tsi0_ch6 lcd_p1/ adc0_se9/ tsi0_ch6 ptb1 i2c0_sda tpm1_ch1 lcd_p1 g9 55 e7 37 ptb2 lcd_p2/ adc0_se12/ tsi0_ch7 lcd_p2/ adc0_se12/ tsi0_ch7 ptb2 i2c0_scl tpm2_ch0 lcd_p2 g8 56 e8 38 ptb3 lcd_p3/ adc0_se13/ tsi0_ch8 lcd_p3/ adc0_se13/ tsi0_ch8 ptb3 i2c0_sda tpm2_ch1 lcd_p3 e11 57 ptb7 lcd_p7 lcd_p7 ptb7 lcd_p7 d11 58 ptb8 lcd_p8 lcd_p8 ptb8 spi1_pcs0 extrg_in lcd_p8 e10 59 ptb9 lcd_p9 lcd_p9 ptb9 spi1_sck lcd_p9 d10 60 ptb10 lcd_p10 lcd_p10 ptb10 spi1_pcs0 lcd_p10 c10 61 ptb11 lcd_p11 lcd_p11 ptb11 spi1_sck lcd_p11 b10 62 e6 39 ptb16 lcd_p12/ tsi0_ch9 lcd_p12/ tsi0_ch9 ptb16 spi1_mosi uart0_rx tpm_ clkin0 spi1_miso lcd_p12 e9 63 d7 40 ptb17 lcd_p13/ tsi0_ch10 lcd_p13/ tsi0_ch10 ptb17 spi1_miso uart0_tx tpm_ clkin1 spi1_mosi lcd_p13 d9 64 d6 41 ptb18 lcd_p14/ tsi0_ch11 lcd_p14/ tsi0_ch11 ptb18 tpm2_ch0 i2s0_tx_ bclk lcd_p14 c9 65 c7 42 ptb19 lcd_p15/ tsi0_ch12 lcd_p15/ tsi0_ch12 ptb19 tpm2_ch1 i2s0_tx_fs lcd_p15 f10 66 ptb20 lcd_p16 lcd_p16 ptb20 cmp0_out lcd_p16 f9 67 ptb21 lcd_p17 lcd_p17 ptb21 lcd_p17 f8 68 ptb22 lcd_p18 lcd_p18 ptb22 lcd_p18 e8 69 ptb23 lcd_p19 lcd_p19 ptb23 lcd_p19 pinout 52 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 121 bga 100 lqfp 64 bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 b9 70 d8 43 ptc0 lcd_p20/ adc0_se14/ tsi0_ch13 lcd_p20/ adc0_se14/ tsi0_ch13 ptc0 extrg_in audiousb_ sof_out cmp0_out i2s0_txd0 lcd_p20 d8 71 c6 44 ptc1/ llwu_p6/ rtc_clkin lcd_p21/ adc0_se15/ tsi0_ch14 lcd_p21/ adc0_se15/ tsi0_ch14 ptc1/ llwu_p6/ rtc_clkin i2c1_scl tpm0_ch0 i2s0_txd0 lcd_p21 c8 72 b7 45 ptc2 lcd_p22/ adc0_se11/ tsi0_ch15 lcd_p22/ adc0_se11/ tsi0_ch15 ptc2 i2c1_sda tpm0_ch1 i2s0_tx_fs lcd_p22 b8 73 c8 46 ptc3/ llwu_p7 lcd_p23 lcd_p23 ptc3/ llwu_p7 uart1_rx tpm0_ch2 clkout i2s0_tx_ bclk lcd_p23 f7 74 e3 47 vss vss vss e7 e4 vdd vdd vdd a11 75 c5 48 vll3 vll3 vll3 a10 76 a6 49 vll2 vll2 vll2/ lcd_p4 ptc20 lcd_p4 a9 77 b5 50 vll1 vll1 vll1/ lcd_p5 ptc21 lcd_p5 b11 78 b4 51 vcap2 vcap2 vcap2/ lcd_p6 ptc22 lcd_p6 c11 79 a5 52 vcap1 vcap1 vcap1/ lcd_p39 ptc23 lcd_p39 a8 80 b8 53 ptc4/ llwu_p8 lcd_p24 lcd_p24 ptc4/ llwu_p8 spi0_pcs0 uart1_tx tpm0_ch3 i2s0_mclk lcd_p24 d7 81 a8 54 ptc5/ llwu_p9 lcd_p25 lcd_p25 ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 cmp0_out lcd_p25 c7 82 a7 55 ptc6/ llwu_p10 lcd_p26/ cmp0_in0 lcd_p26/ cmp0_in0 ptc6/ llwu_p10 spi0_mosi extrg_in i2s0_rx_ bclk spi0_miso i2s0_mclk lcd_p26 b7 83 b6 56 ptc7 lcd_p27/ cmp0_in1 lcd_p27/ cmp0_in1 ptc7 spi0_miso audiousb_ sof_out i2s0_rx_fs spi0_mosi lcd_p27 a7 84 ptc8 lcd_p28/ cmp0_in2 lcd_p28/ cmp0_in2 ptc8 i2c0_scl tpm0_ch4 i2s0_mclk lcd_p28 d6 85 ptc9 lcd_p29/ cmp0_in3 lcd_p29/ cmp0_in3 ptc9 i2c0_sda tpm0_ch5 i2s0_rx_ bclk lcd_p29 c6 86 ptc10 lcd_p30 lcd_p30 ptc10 i2c1_scl i2s0_rx_fs lcd_p30 c5 87 ptc11 lcd_p31 lcd_p31 ptc11 i2c1_sda i2s0_rxd0 lcd_p31 b6 88 ptc12 lcd_p32 lcd_p32 ptc12 tpm_ clkin0 lcd_p32 a6 89 ptc13 lcd_p33 lcd_p33 ptc13 tpm_ clkin1 lcd_p33 d5 90 ptc16 lcd_p36 lcd_p36 ptc16 lcd_p36 c4 91 ptc17 lcd_p37 lcd_p37 ptc17 lcd_p37 b4 92 ptc18 lcd_p38 lcd_p38 ptc18 lcd_p38 d4 93 c3 57 ptd0 lcd_p40 lcd_p40 ptd0 spi0_pcs0 tpm0_ch0 lcd_p40 pinout kinetis kl46 sub-family, rev5 08/2014. 53 freescale semiconductor, inc. 121 bga 100 lqfp 64 bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 d3 94 a4 58 ptd1 lcd_p41/ adc0_se5b lcd_p41/ adc0_se5b ptd1 spi0_sck tpm0_ch1 lcd_p41 c3 95 c2 59 ptd2 lcd_p42 lcd_p42 ptd2 spi0_mosi uart2_rx tpm0_ch2 spi0_miso lcd_p42 b3 96 b3 60 ptd3 lcd_p43 lcd_p43 ptd3 spi0_miso uart2_tx tpm0_ch3 spi0_mosi lcd_p43 a3 97 a3 61 ptd4/ llwu_p14 lcd_p44 lcd_p44 ptd4/ llwu_p14 spi1_pcs0 uart2_rx tpm0_ch4 lcd_p44 a2 98 c1 62 ptd5 lcd_p45/ adc0_se6b lcd_p45/ adc0_se6b ptd5 spi1_sck uart2_tx tpm0_ch5 lcd_p45 b2 99 b2 63 ptd6/ llwu_p15 lcd_p46/ adc0_se7b lcd_p46/ adc0_se7b ptd6/ llwu_p15 spi1_mosi uart0_rx spi1_miso lcd_p46 a1 100 a2 64 ptd7 lcd_p47 lcd_p47 ptd7 spi1_miso uart0_tx spi1_mosi lcd_p47 j3 nc nc nc h3 nc nc nc k4 nc nc nc l7 nc nc nc j9 nc nc nc j4 nc nc nc h11 nc nc nc f11 nc nc nc a5 nc nc nc b5 nc nc nc a4 nc nc nc b1 nc nc nc c2 nc nc nc c1 nc nc nc d2 nc nc nc d1 nc nc nc e1 nc nc nc 5.2 kl46 pinouts the following figures show the pinout diagrams for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, ssee kl46 signal multiplexing and pin assignments . pinout 54 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 1 a ptd7 b nc c nc d nc e nc f usb0_dp g vout33 h pte16 j pte18 k pte20 1 l pte22 2 ptd5 ptd6/ llwu_p15 nc nc pte2 usb0_dm vregin pte17 pte19 pte21 2 pte23 3 ptd4/ llwu_p14 ptd3 ptd2 ptd1 pte1 pte6 vss nc nc pta6 3 pte29 4 nc ptc18 ptc17 ptd0 pte0 pte3 pte5 pta7 nc nc 4 pte31 5 nc nc ptc11 ptc16 vdd vdda vrefh pte24 pte25 pte30 5 vss 6 ptc13 ptc12 ptc10 ptc9 vdd vssa vrefl pte26 pta0 vdd 6 vss 7 ptc8 ptc7 ptc6/ llwu_p10 ptc5/ llwu_p9 vdd vss vss pte4 pta2 pta5 7 nc 8 ptc4/ llwu_p8 ptc3/ llwu_p7 ptc2 ptc1/ llwu_p6/ rtc_clkin ptb23 ptb22 ptb3 pta1 pta4 pta12 8 pta13 9 vll1 ptc0 ptb19 ptb18 ptb17 ptb21 ptb2 pta3 nc pta14 9 pta15 10 vll2 ptb16 ptb11 ptb10 ptb9 ptb20 ptb1 pta17 pta16 vss 10 vdd 11 a vll3 b vcap2 c vcap1 d ptb8 e ptb7 f nc g ptb0/ llwu_p5 h nc j pta20 k pta19 11 l pta18 figure 23. kl46 121-pin bga pinout diagram pinout kinetis kl46 sub-family, rev5 08/2014. 55 freescale semiconductor, inc. 60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pte22 pte21 pte20 pte19 pte18 pte17 pte16 vregin vout33 usb0_dm usb0_dp vss vdd pte6 pte5 pte4 pte3 pte2 pte1 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vll3 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 ptb11 ptb10 ptb9 ptb8 ptb7 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 25 24 23 22 21 vssa vrefl vrefh vdda pte23 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6/llwu_p15 vcap1 vcap2 vll1 vll2 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13 pta12 pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 pte26 pte25 pte24 vdd vss pte31 pte30 pte29 98 ptd5 97 ptd4/llwu_p14 96 ptd3 95 ptd2 94 ptd1 93 ptd0 92 ptc18 91 ptc17 90 ptc16 89 ptc13 88 ptc12 80 ptc4/llwu_p8 ptc5/llwu_p9 ptc6/llwu_p10 81 82 83 ptc7 84 ptc8 85 ptc9 86 ptc10 87 ptc11 100 ptd7 figure 24. kl46 100-pin lqfp pinout diagram pinout 56 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 1 a pte0 b pte1 c ptd5 d usb0_dm e usb0_dp f pte21 g pte20 1 h pte29 2 ptd7 ptd6/ llwu_p15 ptd2 vregin vout33 pte23 pte22 2 pte30 3 ptd4/ llwu_p14 ptd3 ptd0 pta0 vss vssa vrefl 3 pte31 4 ptd1 vcap2 vss pta1 vdd vdda vrefh 4 pte24 5 vcap1 vll1 vll3 pta3 pta2 pta5 pta4 5 pte25 6 vll2 ptc7 ptc1/ llwu_p6/ rtc_clkin ptb18 ptb16 ptb1 pta13 6 pta12 7 ptc6/ llwu_p10 ptc2 ptb19 ptb17 ptb2 ptb0/ llwu_p5 vdd 7 vss 8 a ptc5/ llwu_p9 b ptc4/ llwu_p8 c ptc3/ llwu_p7 d ptc0 e ptb3 f pta20 g pta19 8 h pta18 figure 25. kl46 64-pin bga pinout diagram pinout kinetis kl46 sub-family, rev5 08/2014. 57 freescale semiconductor, inc. pte24 pte31 pte30 pte29 vssa vrefl vrefh vdda pte23 pte22 pte21 pte20 vregin vout33 usb0_dm usb0_dp vss vdd pte1 pte0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2 ptd1 ptd0 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vcap1 vcap2 vll1 vll2 vll3 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptc0 ptb19 ptb18 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta18 vss vdd pta13 pta12 pta5 pta4 pta3 pta2 pta1 pta0 pte25 figure 26. kl46 64-pin lqfp pinout diagram 6 ordering parts ordering parts 58 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: pkl46 and mkl46 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q kl## a fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): table 42. part number fields descriptions field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kl## kinetis family ? kl46 a key attribute ? z = cortex-m0+ fff program flash memory size ? 128 = 128 kb ? 256 = 256 kb r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 pp package identifier ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) table continues on the next page... part identification kinetis kl46 sub-family, rev5 08/2014. 59 freescale semiconductor, inc. table 42. part number fields descriptions (continued) field description values ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 mapbga (8 mm x 8 mm) cc maximum cpu frequency (mhz) ? 4 = 48 mhz n packaging type ? r = tape and reel 7.4 example this is an example part number: mkl46z256vmc4 8 terminology and guidelines 8.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 example this is an example of an operating requirement: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 8.2 definition: operating behavior unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. terminology and guidelines 60 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 8.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 8.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 8.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v terminology and guidelines kinetis kl46 sub-family, rev5 08/2014. 61 freescale semiconductor, inc. 8.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 8.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. terminology and guidelines 62 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. 8.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 8.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines kinetis kl46 sub-family, rev5 08/2014. 63 freescale semiconductor, inc. 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 8.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): table 43. typical value conditions symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 9 revision history the following table provides a revision history for this document. table 44. revision history rev. no. date substantial changes 3 3/2014 ? updated the front page and restructured the chapters ? updated voltage and current operating behaviors ? updated emc radiated emissions operating behaviors ? updated power mode transition operating behaviors table continues on the next page... revision history 64 kinetis kl46 sub-family, rev5 08/2014. freescale semiconductor, inc. table 44. revision history (continued) rev. no. date substantial changes ? updated capacitance attributes ? updated footnote in the device clock specifications ? added thermal attributes of 64-pin mapbga in the thermal attributes ? added v refh and v refl in the 16-bit adc electrical characteristics ? updated footnote to the v dacr in the 12-bit dac operating requirements ? updated i loadrun and i lim in the usb vreg electrical specifications ? added inter-integrated circuit interface (i2c) timing 4 5/2014 ? updated power consumption operating behaviors ? updated usb electrical specifications ? updated definition: operating behavior 5 08/2014 ? updated related source in the front page ? updated power consumption operating behaviors ? updated the note in usb electrical specifications revision history kinetis kl46 sub-family, rev5 08/2014. 65 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support document number KL46P121M48SF4 revision 5 08/2014 ? 2012-2014 freescale semiconductor, inc. information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale, freescale logo, energy efficient solutions logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. |
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